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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:08:29 09/24/2013 
-- Design Name: 
-- Module Name:    left_shifter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity left_shifter is
    Port (	input : in  STD_LOGIC_VECTOR (31 downto 0);
				shiftValue : in STD_LOGIC_VECTOR (4 downto 0);
				output : out  STD_LOGIC_VECTOR (31 downto 0));
end left_shifter;

architecture Behavioral of left_shifter is
	signal outputIntermediate1 : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
	signal outputIntermediate2 : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
	signal outputIntermediate4 : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
	signal outputIntermediate8 : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
begin
	outputIntermediate1 <= 	input when shiftValue(0) = '0' else
										input(30 downto 0) & '0';
	outputIntermediate2 <= 	outputIntermediate1 when shiftValue(1) = '0' else
										input(29 downto 0) & "00";
	outputIntermediate4 <= 	outputIntermediate2 when shiftValue(2) = '0' else
										input(27 downto 0) & "0000";
	outputIntermediate8 <= 	outputIntermediate4 when shiftValue(3) = '0' else
										input(23 downto 0) & "00000000";
	output <= 	outputIntermediate8 when shiftValue(4) = '0' else
										input(15 downto 0) & "0000000000000000";
end Behavioral;
